В Сан-Франциско в январе прошла конференция "ISSCC 2011" (International Solid-State Circuits Conference), на которой Sony представила стратегию развития CMOS-сенсоров ближайшего будущего.
Ниже выкладываю машинный (Google) перевод с японского:
Sony 17,70 pieces of 120 million pixels/sec high-speed CMOS sensor developed
The mainstay of CMOS sensors from CCD camera sensors are moving. CMOS sensor, "high speed" and "low power" because it is accepted, and features. Particularly high speed, "HDR" Art (Casio), "Panorama" swing (Sony), "Night Portrait clear" (Nikon), which also culminated in the use of functions and shooting.
Sony announced at the 2011 ISSCC 17,70 effective megapixel CMOS sensor 120fps
These circumstances, can be read five times the speed of the trend over the past Sony's newly developed CMOS sensor. "The next generation Exmor" can say what digital cameras are currently deployed as well as the CMOS technology it is possible to use a sensor products. In addition to high-speed continuous shooting is possible to now over, rolling it possible to reduce distortion when shooting video.
Held in February in San Francisco LSI International Conference "ISSCC 2011" (International Solid-State Circuits Conference) sponsored&published by IEEE.
This new sensor, said image division Tooyama Takayuki senior product manager, Sony Semiconductor Group (left), Hideo Nomura, director of business development division and the image (right) listened to the story
This prototype is effective megapixels 17,70 Mpix
(8192 × 2160 pixels) and 120fps, 12bit CMOS sensor can be read. In the case of possible output 60fps 14bit.
The size is 24.3 × 12.8mm (diagonal 27.5mm).
The pixel pitch of 4.2 × 4.2μm.
8k2K sensor itself, but the vertical resolution of the interpolation carried out at a later stage can output 8k4k.
As a first target, NHK Super Hi-Vision assuming promoted. Has about 16 times the information of the current full HD, it is known to be used for broadcasting in the near future. However, the technology itself that it can expand this flexibility without sticking to the size and number of pixels. Therefore, it can make a variety of specifications for digital cameras, ranging from mobile phones. That can be applied to back-illuminated. For the external sales, "Some things in-house, as I think some public-facing" (Mr. Nomura) was.
"This sensor is about the same size and interchangeable lens type digital camera.] Example [α55 (16.2 megapixels effective) is 10 Even though a fast continuous shooting / sec. Indiscriminately because some mechanical shutter involving both the sensor is said to involve the speed and power consumption. α55 has 10 sensors / second set (the final product) is a specification that can be put, this sensor 120 frames/sec would be taken "(Mr. Toyama).
This time, the power consumption of 3W drive containing a sensor at about 120fps. This is the spec that it be included on a common set of heat dissipation if Nae. The announcement made at levels close to the practical use of these sensors, it is of great significance to this. The random noise and *, longitudinal fixed pattern noise, especially noise and it has been almost invisible level.
"If we will have a variety of techniques employed, can not of course far faster. And even temporarily increase the speed, could not heat up too much power consumption, a noisy image" (Mr. Toyama .)
The new sensor production start date has not been disclosed. The plan as it is a product newly developed sensor had not been cleared. But plans to expand this technology into a product internally so there is, he said that in recent years due in various products using this technology. "This next generation technology based on its ability to offer the entire Exmor. So far in the future technology is not at all have" (Mr. Nomura).
CMOS sensor still has room for growth
LSI to handle the whole ISSCC There are many categories, in 2011 there were 11 presentations related to the image sensor. That it more than ever the number of previous years. Then the paper will be presented, the issue with the ranking scores for each expert. ISSCC The "Olympics of the semiconductor," he called Yuen. This new sensor good articles about the reputation of the announcement, interest in the audience asked many questions and seems to be high.
Semiconductor Group, Atsugi Technology Center enters (Atsugi Tec. Atsugi, Kanagawa)
According to Sony, it has also come to ask that the paper wants to explain from outside (strictly, "the technology" a question about the stage in a study of the device is not used.) Papers ISSCC 2011, adopted by 211 in total. It was selected from 669 posts. There is only referred to the Olympics, must participate ability is just paper.
ISSCC in addition to "cash" needed as well. The only theory that can prove to be rather critical. "We also made some few took the average. Because there is the assumption that future products will expand, not the data out of data and only one champion is not" (Mr. Toyama) .
This sensor is the same as the previous 90nm process rule was adopted. The circuit has been devised, the manufacturing process requires no special processes, which can meet existing facilities. Sony also made a prototype of this plant. Mr. Toyama said, "production costs are almost unchanged with the idea of conventional" trying to.
Nomura said, "As a manufacturer Sony sensor technology have made until it put the photodiode circuit. CMOS sensor is not only a simple process, proved that there is still room for ingenuity in the circuit. Sensor it's still able to develop. I want to make a world of new technology, new cameras, "he said.
Both speed and low power consumption
Sony, ISSCC in 2006 A / D converter (ADC) to the slope of a single column "ADC" was released. After "Exmor" has become a commodity. This time, the column ADC achieves high-speed readout and low power consumption while taking advantage of a review of the circuit configuration. And on-chip sensors, such as this photodiodes are using the same as before.
At the time of the year 2006, Sony megapixel 600 60fps and 180fps column ADC 280 megapixels CMOS type sensor announced. "The circuit portion was sold to the other with reduced noise and fixed pattern noise significantly longitudinal" (Mr. Nomura). Announced today that shape the evolution of technology and five years.
120fps at 1,770 million pixels, the data rate of 34.8Gbps (4.35GB / s) equivalent to five times conventional. Figure is far above the trend line has continued to improve data rates in the industry so far. Yet D range (S / N ratio) has secured an average Traditional 77.6dB, and loss of quality compared to previous products, he said.
Samples taken by the prototype sensor (courtesy of Sony). If you notice a fan blade, 48fps but has produced no distortion I can see rolling out in 120fps little effect in
This highlights the "high-speed ADC" and "high-speed digital data read circuit," but two. Developed the following three technologies to achieve this:
Dual Row Readout (DRR)
Hybrid Column Counters
SLVS-EC (Scalable Low Voltage Signaling with Embedded Clock)
CMOS and the easy flow of the signals on the sensor, the column of charge analog → light entering the photodiode ADC → sent to the ADC output to the outside of the image sensor to digital data →'s digital data to the count, and so on. In technology, we look at each in turn.
First "Dual Row Readout" The photodiode signals when the ADC transfer counter, it will read the two lines approach. Common Sensor was to scan the existing line by line. This image area is divided into upper and lower areas of the upper half of the ADC is placed on the columns, as well as the lower half of the area was placed under the column ADC signals simultaneously. Half the time was now transferred from the photodiode.
In addition, we have adopted an array of pixels is rotated 45 degrees. The company's technology "ClearVid" CMOS equipped with sensors and a pattern similar to that effectiveness is easy to devise a vertical pixel interpolation.
Then, the column ADC receives the analog signal is active in the "Hybrid Column Counters". I read part of a fast liver. To perform high-speed AD conversion, you need to move faster clock counter. But on the clock and we had a problem working as a counter right away after it slowed down in the middle of the clock signal is transmitted. Clock signal line for communicating, many flip-flops hanging (constituting a counter circuit), who had been to the load. ADC column because it requires the same number of counters to the number of pixels horizontally, which had been difficult enough to accelerate high-resolution clock.
To solve this problem, all bundled 15bit hundreds of lower 5 bits of a "Lower-bit Counter" was arranged. Technology is shared by a number of counters in one column was the last to arrive at the counter at a fast clock signal thereby. 594MHz clock frequency from a conventional can be raised to 2,376 MHz were about four times faster than 2.6μs to count time from one frame 10.3μs.
Tied for the low-bit, high bit-side due to the way it was implemented "Hybrid" with the name. Power-saving improvements were also realized this. Lower bits consumes significant power was always moving because they carry a lot of time counting, Lower-bit Counter with a power that the traditional / 3-1 / 4 decreased.
The ADC way, DNL (Differential Non Linearity) called "gap between the theoretical steps and actual steps" that contains the error. Without this shift at all (ADC ideal if you work) DNL is a 0, in fact can not be zero. If the dispersion of the histogram DNL, ± 0.5LSB (LSB: least significant bit) and can not be guaranteed beyond the scope of the accuracy of the ADC as. In this Hybrid Column Counters -0.3 +0.45 and fits, "not only fast, but that can count properly" (Mr. Toyama) be.
Although the ADC and thus faster, interface is slow sending out the digital data generated by the sensor does not make sense. So sending in the form of digital data signals with embedded timing clock "Enbededdokurokku" was adopted. This is, "SLVS-EC" Using interface was placed at four corners of the sensor. Rate per channel is 2.376Gbps (297MB / s). For a total of 16 channels has become a four lane in one place.
The Embeded PCI Express, including technology that is used in many of the serial interface. Signal skew (strain) does not occur in theory, are in favor of speed and long-distance transport. This time, resulting in total PCI Express1.1 faster than the 16-lane interface.
These high-speed interface, the performance is decided by the distance coming. This 30cm jitter even if the internal wiring is drawn 0.1UI (unit interval), a period of time kept to about 1 420.87ps 10 percent. The error rate of 10 -15 has been achieved with lower power. In the chip was reduced also set up a reflected signal termination of 50Ω.
"Jitter performance can hardly say. About three orders of magnitude better accuracy than commercial" (Mr. Toyama).
Most low voltage 0.4V interface and suppressed power consumption 200mW.
Nomura says is "embedded in the specification as the image sensor technology that can withstand being used in" general terms and Sony's great advantages.
Ниже выкладываю машинный (Google) перевод с японского:
Sony 17,70 pieces of 120 million pixels/sec high-speed CMOS sensor developed
The mainstay of CMOS sensors from CCD camera sensors are moving. CMOS sensor, "high speed" and "low power" because it is accepted, and features. Particularly high speed, "HDR" Art (Casio), "Panorama" swing (Sony), "Night Portrait clear" (Nikon), which also culminated in the use of functions and shooting.
These circumstances, can be read five times the speed of the trend over the past Sony's newly developed CMOS sensor. "The next generation Exmor" can say what digital cameras are currently deployed as well as the CMOS technology it is possible to use a sensor products. In addition to high-speed continuous shooting is possible to now over, rolling it possible to reduce distortion when shooting video.
Held in February in San Francisco LSI International Conference "ISSCC 2011" (International Solid-State Circuits Conference) sponsored&published by IEEE.
This prototype is effective megapixels 17,70 Mpix
(8192 × 2160 pixels) and 120fps, 12bit CMOS sensor can be read. In the case of possible output 60fps 14bit.
The size is 24.3 × 12.8mm (diagonal 27.5mm).
The pixel pitch of 4.2 × 4.2μm.
8k2K sensor itself, but the vertical resolution of the interpolation carried out at a later stage can output 8k4k.
As a first target, NHK Super Hi-Vision assuming promoted. Has about 16 times the information of the current full HD, it is known to be used for broadcasting in the near future. However, the technology itself that it can expand this flexibility without sticking to the size and number of pixels. Therefore, it can make a variety of specifications for digital cameras, ranging from mobile phones. That can be applied to back-illuminated. For the external sales, "Some things in-house, as I think some public-facing" (Mr. Nomura) was.
"This sensor is about the same size and interchangeable lens type digital camera.] Example [α55 (16.2 megapixels effective) is 10 Even though a fast continuous shooting / sec. Indiscriminately because some mechanical shutter involving both the sensor is said to involve the speed and power consumption. α55 has 10 sensors / second set (the final product) is a specification that can be put, this sensor 120 frames/sec would be taken "(Mr. Toyama).
This time, the power consumption of 3W drive containing a sensor at about 120fps. This is the spec that it be included on a common set of heat dissipation if Nae. The announcement made at levels close to the practical use of these sensors, it is of great significance to this. The random noise and *, longitudinal fixed pattern noise, especially noise and it has been almost invisible level.
"If we will have a variety of techniques employed, can not of course far faster. And even temporarily increase the speed, could not heat up too much power consumption, a noisy image" (Mr. Toyama .)
The new sensor production start date has not been disclosed. The plan as it is a product newly developed sensor had not been cleared. But plans to expand this technology into a product internally so there is, he said that in recent years due in various products using this technology. "This next generation technology based on its ability to offer the entire Exmor. So far in the future technology is not at all have" (Mr. Nomura).
CMOS sensor still has room for growth
LSI to handle the whole ISSCC There are many categories, in 2011 there were 11 presentations related to the image sensor. That it more than ever the number of previous years. Then the paper will be presented, the issue with the ranking scores for each expert. ISSCC The "Olympics of the semiconductor," he called Yuen. This new sensor good articles about the reputation of the announcement, interest in the audience asked many questions and seems to be high.
According to Sony, it has also come to ask that the paper wants to explain from outside (strictly, "the technology" a question about the stage in a study of the device is not used.) Papers ISSCC 2011, adopted by 211 in total. It was selected from 669 posts. There is only referred to the Olympics, must participate ability is just paper.
ISSCC in addition to "cash" needed as well. The only theory that can prove to be rather critical. "We also made some few took the average. Because there is the assumption that future products will expand, not the data out of data and only one champion is not" (Mr. Toyama) .
This sensor is the same as the previous 90nm process rule was adopted. The circuit has been devised, the manufacturing process requires no special processes, which can meet existing facilities. Sony also made a prototype of this plant. Mr. Toyama said, "production costs are almost unchanged with the idea of conventional" trying to.
Nomura said, "As a manufacturer Sony sensor technology have made until it put the photodiode circuit. CMOS sensor is not only a simple process, proved that there is still room for ingenuity in the circuit. Sensor it's still able to develop. I want to make a world of new technology, new cameras, "he said.
Both speed and low power consumption
Sony, ISSCC in 2006 A / D converter (ADC) to the slope of a single column "ADC" was released. After "Exmor" has become a commodity. This time, the column ADC achieves high-speed readout and low power consumption while taking advantage of a review of the circuit configuration. And on-chip sensors, such as this photodiodes are using the same as before.
At the time of the year 2006, Sony megapixel 600 60fps and 180fps column ADC 280 megapixels CMOS type sensor announced. "The circuit portion was sold to the other with reduced noise and fixed pattern noise significantly longitudinal" (Mr. Nomura). Announced today that shape the evolution of technology and five years.
120fps at 1,770 million pixels, the data rate of 34.8Gbps (4.35GB / s) equivalent to five times conventional. Figure is far above the trend line has continued to improve data rates in the industry so far. Yet D range (S / N ratio) has secured an average Traditional 77.6dB, and loss of quality compared to previous products, he said.
This highlights the "high-speed ADC" and "high-speed digital data read circuit," but two. Developed the following three technologies to achieve this:
Dual Row Readout (DRR)
Hybrid Column Counters
SLVS-EC (Scalable Low Voltage Signaling with Embedded Clock)
CMOS and the easy flow of the signals on the sensor, the column of charge analog → light entering the photodiode ADC → sent to the ADC output to the outside of the image sensor to digital data →'s digital data to the count, and so on. In technology, we look at each in turn.
First "Dual Row Readout" The photodiode signals when the ADC transfer counter, it will read the two lines approach. Common Sensor was to scan the existing line by line. This image area is divided into upper and lower areas of the upper half of the ADC is placed on the columns, as well as the lower half of the area was placed under the column ADC signals simultaneously. Half the time was now transferred from the photodiode.
In addition, we have adopted an array of pixels is rotated 45 degrees. The company's technology "ClearVid" CMOS equipped with sensors and a pattern similar to that effectiveness is easy to devise a vertical pixel interpolation.
Then, the column ADC receives the analog signal is active in the "Hybrid Column Counters". I read part of a fast liver. To perform high-speed AD conversion, you need to move faster clock counter. But on the clock and we had a problem working as a counter right away after it slowed down in the middle of the clock signal is transmitted. Clock signal line for communicating, many flip-flops hanging (constituting a counter circuit), who had been to the load. ADC column because it requires the same number of counters to the number of pixels horizontally, which had been difficult enough to accelerate high-resolution clock.
To solve this problem, all bundled 15bit hundreds of lower 5 bits of a "Lower-bit Counter" was arranged. Technology is shared by a number of counters in one column was the last to arrive at the counter at a fast clock signal thereby. 594MHz clock frequency from a conventional can be raised to 2,376 MHz were about four times faster than 2.6μs to count time from one frame 10.3μs.
Tied for the low-bit, high bit-side due to the way it was implemented "Hybrid" with the name. Power-saving improvements were also realized this. Lower bits consumes significant power was always moving because they carry a lot of time counting, Lower-bit Counter with a power that the traditional / 3-1 / 4 decreased.
The ADC way, DNL (Differential Non Linearity) called "gap between the theoretical steps and actual steps" that contains the error. Without this shift at all (ADC ideal if you work) DNL is a 0, in fact can not be zero. If the dispersion of the histogram DNL, ± 0.5LSB (LSB: least significant bit) and can not be guaranteed beyond the scope of the accuracy of the ADC as. In this Hybrid Column Counters -0.3 +0.45 and fits, "not only fast, but that can count properly" (Mr. Toyama) be.
Although the ADC and thus faster, interface is slow sending out the digital data generated by the sensor does not make sense. So sending in the form of digital data signals with embedded timing clock "Enbededdokurokku" was adopted. This is, "SLVS-EC" Using interface was placed at four corners of the sensor. Rate per channel is 2.376Gbps (297MB / s). For a total of 16 channels has become a four lane in one place.
The Embeded PCI Express, including technology that is used in many of the serial interface. Signal skew (strain) does not occur in theory, are in favor of speed and long-distance transport. This time, resulting in total PCI Express1.1 faster than the 16-lane interface.
These high-speed interface, the performance is decided by the distance coming. This 30cm jitter even if the internal wiring is drawn 0.1UI (unit interval), a period of time kept to about 1 420.87ps 10 percent. The error rate of 10 -15 has been achieved with lower power. In the chip was reduced also set up a reflected signal termination of 50Ω.
"Jitter performance can hardly say. About three orders of magnitude better accuracy than commercial" (Mr. Toyama).
Most low voltage 0.4V interface and suppressed power consumption 200mW.
Nomura says is "embedded in the specification as the image sensor technology that can withstand being used in" general terms and Sony's great advantages.
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